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The application window is expected to close on: 07/01/2026Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.<h2>Meet the Team</h2>The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.<h2>Your Impact</h2><ul><li>Fullchip Floorplan by understanding the architecture of the design and IP placement constraints</li><li>Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan</li><li>Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning</li><li>RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.</li><li>Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.</li><li>Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.</li><li>Proficiency in low-power design methodo

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Senior ASIC Physical Design Technical Lead

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