Hardware SI/PI Engineering Senior Technical Leader | SI/PI, PCB, Package, VNA, TDR, HFSS, ADS, Allegro, PAM4 SERDES | 12+ years, Bangalore

About this role

<h2><b>Meet the Team</b><br />At Cisco's Common Hardware Group (CHG), our Signal & Power Integrity (SI/PI) team is where physics meets innovation. We design and analyze the high-speed interconnects and power distribution networks that fuel Cisco's next-generation Switch, Router, and AI/ML platforms.<br />We're looking for a Technical Lead, Signal & Power Integrity who's passionate about solving complex challenges across ASIC, package, PCB, and system levels, and who thrives at the intersection of deep technical problem-solving and hands-on mentorship.<br />This role offers a chance to shape leading-edge networking and compute systems while working alongside some of the most talented engineers in the industry-system architects, ASIC designers, packaging experts, and fellow SI/PI specialists-driving ideas from simulation all the way to product launch.<br /> </h2><h2><b>Your Impact</b></h2><ul><li><h2>Model and simulate high-speed links, including SerDes, IC package, and system interconnects</h2></li><li><h2>Analyze and model power delivery networks and perform EM modeling of complex 3D structures</h2></li><li><h2>Lead pre- and post-layout signal integrity analysis for both PCB and package designs</h2></li><li><h2>Define stack-up strategy, PCB materials, and collaborate with vendors on DFM and manufacturability</h2></li><li><h2>Write SI/PI design guidelines, test plans, and validation reports</h2></li><li><h2>Support prototype bring-up, validation, and troubleshooting in the lab</h2></li><li><h2>Partner closely with HW design, Mechanical, Power, EMC, and Diagnostics teams to deliver world-class hardware</h2></li><li><h2>Mentor and guide junior SI/PI engineers, fostering a culture of learning and technical excellence</h2></li><li><h2>Drive continuous improvement of simulation flows, design processes, and methodologies</h2></li><li><h2>Lead system-level investigations spanning ASIC, package, and board domains</h2></li><li><h2>Contribute to our SI/PI technology roadmap-ev

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