ASIC - Signal and Power Integrity Technical Leader - 10 to 16 Years - Bangalore/Chennai

About this role

<h2>MEET THE TEAM</h2><p>Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio

</p><p></p><p>We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!</p><h2><br />YOUR IMPACT</h2><p>We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead our Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging to be deployed in a range of Cisco platforms

</p><ul><li><p>Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.</p></li><li><p> Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.</p></li><li><p>Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.</p></li><li><p>Collaborate with system partners, vendors, and design leads to achieve combined power and signal i

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