ASIC Layout Engineer - Analog, High speed IP - 8 to 11 years - Bangalore

About this role

<h2>What You'll Do</h2><p>We are looking for a talented and motivated <b>Layout Lead</b> to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.</p><p>You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.</p><h2>Specific responsibilities include: </h2><ul><li>Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks </li><li>Participate in block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs </li><li>Collaborate with circuit designers to translate schematics and performance targets into optimized physical layouts </li><li>Optimize layouts for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability </li><li>Ensure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements) </li><li>Assist in integration across analog, digital, and high-speed domains, including support for top-level assembly of SerDes, PAM4 paths, clocking, and control logic </li><li>Review post-layout extraction results and support simulation closure </li><li>Follow best practices for symmetry, shielding, isolation, and signal integrity </li><li>Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration </li><li>Identify and help resolve layout-related issues impacting performance, yield, or

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