ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)

About this role

<h2><b>Meet the Team</b></h2><p>Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.</p><p>You will work with Cisco's outstanding Silicon Photonics team

Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.</p><h2></h2><h2>What You'll Do</h2><p>The Digital Design Lead for the Client Optics Group (COG) provides essential technical leadership in the development of digital logic for silicon photonics, ensuring high-performance outcomes for 100G, 200G, and 400G optical interconnects. This role involves managing the full ASIC lifecycle, from architectural conception and RTL-based design of CPU subsystems and data path interfaces to tapeout and post-silicon production support, while overseeing the integration of digital logic with analog and mixed-signal blocks to ensure the reliability of Co-Packaged Optics and silicon photonics modules.</p><p></p><p>Candidates must possess comprehensive expertise in high-speed optical interconnects and mastery of the complete ASIC/SoC design flow, including DFT, physical design, and verification. Furthermore, the position requires the ability to drive tec

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