Sr Manager Design Development Technical Leadership, HBM

About this role

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design Development Technical Lead (DDTL) is accountable for predictable, timely delivery of HBM design achievements across the design phase of the product lifecycle

This role serves as the single‑threaded technical program owner for HBM Design execution, coordinating across DRAM, base die, test vehicles, interposers, IP, and foundries(internal and external). Operating within Micron’s Heterogeneous Integration Group (HIG), the DDTL leads cross‑functional execution, manages design dependencies and risks, owns change control, and represents HBM Design in PDT and executive forums to ensure schedule, cost, quality, and product objectives are met Responsibilities Design Program Ownership Own end‑to‑end execution of on schedule delivery of HBM design achievements, ensuring alignment across DRAM, base die, test chips, PTVs, interposers, and sustaining designs. Be the primary design representative in PDT and executive reviews

Define and manage cross‑functional dependencies across all collaborators Lead execution governance, including DDTL Syncs and Design Program Reviews (DPRs), providing clear executive‑level status, risks, and decision asks. Own and operate formal Change Control Board (CCB) processes, ensuring disciplined POR management, cost/schedule awareness, and traceability. Maintain a comprehensive design risk register

Proactively identify risks, lead mitigation workgroups, define checkpoints, and bring up issues through governance forums as required. Capture and institutionalize lessons learned to improve future program execution. Drive early engagement during architecture and design phases to enable shift‑left risk mitigation

Lead initiatives to optimize die size,

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