Senior Serdes System Design Engineer/Architect

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+

The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities. You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production. You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF

Responsibilities include: Develop channel models and run simulations to help define Serdes architecture Define and document signal processing block requirements, architecture, and lab test plan Develop bit-exact MATLAB and C/C++ system models for simulation and verification Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs Work with the design team to perform vector matching verification with RTL simulations Develop, test, and debug firmware associated with physical layer functionality Lab testing and debug of Serdes Documentation/application note development and customer support Support marketing group with customer meetings and collateral Job R

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