Senior Physical Design Engineer

About this role

Experience and knowledge on Synthesis, RTL / DFT feedback , Timing Constraints. Responsible for RTL to GDS implementation in Physical Design domain for production flagship projects. Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners

Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. Demonstrate technical expertise across various domains of Physical Design & Timing Signoff. Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA)

Drive end-to-end execution from synthesis through place-and-route for block execution, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes. Clear communications on project status & planning

Proven track record in mentoring, influencing teams, and driving alignment through clear and effective communication. Analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python. SCHIE #CSME #Siliconjobs #CCDO Silicon Engineering IC4 - The typical base pay range for this role across the U.S

is USD $119,800.00 - $234,700.00 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200.00 - $261,000.00 per year. Certain roles may be eligible for benefits and other compensation

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field A

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