Senior Digital Mixed-Signal (DMS) Verification Engineer

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job Description Summary: Join Broadcom, a global technology leader and Fortune 500 powerhouse at the forefront of semiconductor innovation and AI infrastructure. Within our specialized Mixed-Signal ASIC division, we build the critical IP that drives next-generation enterprise storage solutions

We are looking for a Senior DMS Verification Engineer to act as a localized methodology leader and key technical bridge for our worldwide engineering organization. This unique opportunity allows a verification architect to drive quality initiatives, pioneer modern automation (including AI-assisted workflows), and establish robust methodologies across our US and Asia design centers. Responsibilities: ▪️Testbench Architecture: Architect, develop, and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASIC products

▪️Methodology Leadership: Champion verification quality by integrating new methodologies, such as SystemVerilog Assertions (SVA) and UVM/OVM, to reduce mixed-signal validation bottlenecks. ▪️Global Team Liaison: Act as the primary liaison between our local US digital design teams and our worldwide verification teams, translating complex specifications into seamless execution. ▪️Flow Automation: Lead initiatives to explore and integrate modern automation and AI-assisted verification workflows to accelerate testbench generation and debug efficiency

▪️Tape-out Execution: Own verification efforts at both the block and system levels for major tape-out projects, driving functional and code coverage to closure. Core Qualifications: ▪️Experience: 5+ years of hands-on experience in digital verification of mixed-signal ASICs or SoCs. ▪️Verification Methodology: Deep expertise in coverage-driv

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