Senior Design Verification Engineer

About this role

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Full-chip functional verification on Micron’s non-volatile memory design projects You thoroughly understand design specs and develop verification plans for various designs TestBench Development in SystemVerilog targeting complete functionality coverage

Create functional coverage code for assigned features Support of SystemVerilog assertion and coverage-driven methodology Support of design verification methodology improvements Run directed and constrained-random verification tests You will think through design corner cases and be able to write relevant cover points Collaborate with digital design team to debug test cases and deliver functionally accurate designs Close coverage measures to identify verification holes and to show progress towards tape-out Driving innovation into the future Memory generations within a dynamic work environment Minimum Qualifications: Mtech degree in Electrical Engineering or Btech with 2 years’ experience required. Design experience of 2+ years is desirable. 0- 7 of experience developing verification collateral in Verilog, System Verilog and UVM UVM Proficiency is desired Prior work experience with complex coverage driven random constraint UVM environment Putting together complex UVM environments from scratch is a requirement Good knowledge on circuit design, digital logic, and logic verification methodology Understanding on Verilog RTL coding, SystemVerilog object-oriented language Good knowledge on programming language such as C++, and scripting language like TCL and PERL Preferred Skills: Knowledge of Non-volatile memory design is highly desired Experience with mixed-mode design and

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