Senior CPU Power Management Architect
Intel Β· USA - TX - Austin, United States
About this role
Job Details: Job Description: The Role and Impact As a CPU Power Management Architect, you will be at the forefront of Intel's innovation, shaping the future of CPU designs for high-performance computing and low-power products. This role is integral to Intel's mission to deliver cutting-edge solutions that power the world's technology, from advanced data centers to everyday consumer devices. You will play a pivotal role in driving end-to-end CPU Power management architecture specifications, ensuring optimal performance, power efficiency, scalability, and interoperability across hardware and software
Through creative problem-solving and collaboration, you will influence cross-functional roadmaps, define technology targets, and deliver revolutionary CPU architectures that meet diverse market requirements. Key Responsibilities Define end-to-end CPU power management microarchitecture, including the design and specification of hardware mechanisms for dynamic voltage and frequency scaling (DVFS), power state transitions (C-states and P-states), thermal control, hotspot detection and mitigation, droop mitigation, ICCMAX enforcement, reset flow architecture, Machine learning algorithms for power and performance, power delivery and power gating techniques, as well as telemetry and debug capabilities. Explore new approaches and devise novel power management and thermal management solutions that deliver optimized CPUs for multiple segments, from high-performance computing to extreme low-power applications
Identify emerging market trends and translate them into novel features. Collaborate with RTL designers, SoC architects, and firmware/OS teams to ensure power management algorithms are implemented correctly and interface seamlessly with software. Review and influence cross-functional roadmaps and collaborate with architects, design, verification, and validation engineers during project execution
Participate in the post silicon debug and tuning of silicon. You will compare r
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