R&D Digital Design Engineer

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks

These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols. The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs

The day to day tasks for this position include but are not limited to the following: 1) Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips 2) Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems. 3) Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains 4) Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment. 5) Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion The successful

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