Physical Design Timing Engineer (STA)

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions. Key Responsibilities: Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG) Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining

Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows Document best practices and lessons learned to drive continuous improvements in future projects Qualifications: Bachelor’s degree in Electrical Engineering or Computer engineering A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools Exper

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