Physical Design Engineer

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products

More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tapeout. Responsibilities: Own chip floor planning, partition creation, clock tree and delivery of top level partitions Resolve physical design issues related to chip integration and assembly Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team Develop and improve floorplan methodologies using both industry and internal tools Perform technical evaluations of IPs, providing recommendations and assessments to meet design specification Preferred qualifications: Bachelors and 12+ years of experience in top level floorplanning with a focus on die size estimate, partitioning, clocking and pin assignment, or Master's degree in Electrical Engineering and 10+ years of experience in top level floorplanning with a focus on die size estimate, partitioning, clocking and pin assignment Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc) Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience Proven track record with bump planning, RDL routes and multi voltage domain designs Experience with hierarchical design planning, power grid design, structured clocks, top level pipeline placement, custom routes and bump planning Experience in collaborating with design, package and methodology team

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