MTS-RTL Verification Engineer
Micron Technology · Bengaluru, India
About this role
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Own verification strategy and planning; translate specifications into executable verification plans and closure metrics Architect and develop scalable, reusable SystemVerilog/UVM verification environments Drive functional and code coverage closure, including assertions and targeted stimulus Lead debug and issue resolution across verification and design teams Provide verification status, risk assessment, and release readiness updates Ensure verification readiness for high‑speed operation, including initialization, reset, CDC, and mode‑transition scenarios Improve verification methodologies, automation, and regression efficiency Mentor engineers and provide technical guidance consistent with senior‑level expectations Required Qualifications Expert in SystemVerilog and UVM, including verification passionate about detailed testing and constrained‑random testing, Formal Verification Strong fundamentals in clocks, resets, FSMs, CDC, and debug Proven experience verifying high‑speed digital designs in advanced process nodes Hands‑on experience with industry simulators, coverage, and debug tools Scripting proficiency (Python, Perl, or Tcl) for automation and productivity Preferred Exposure to power‑aware verification Experience with high‑speed memory or adjacent subsystems Experience working with global, cross‑site teams Success Indicators Stable, reusable verification environments with clear closure metrics Data‑driven coverage closure with minimal late escapes Early identification and resolution of high‑speed verification risks Effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and supp
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