Mixed Signal Logic Design Engineer

About this role

Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation

Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block. Qualifications: You must possess the below minimum qualifications to be initially considered for this position

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related technical discipline 2+ years of experience with the following technical skills: Proficiency in RTL design and coding using System Verilog and Verilog

Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating. Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs. Experience with hardware simulation tools and methodologies (VCS/Verdi

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