Mixed Signal Design Verification Engineer

About this role

Job Details: Job Description: The Role and Impact As a Mixed Signal Design Verification Engineer in the Power Solutions and Sensors team, you will play a pivotal role in ensuring the functionality and performance of mixed signal logic components critical to Intel's success in delivering critical IPs on advanced process nodes. Leveraging your expertise in mixed signal verification, you will contribute to the development and validation of IPs that meet rigorous microarchitecture specifications, impacting the quality, reliability, and efficiency of Intel's technologies. Your contributions will directly support Intel's mission to drive innovation and deliver best-in-class solutions across its portfolio of products

Key Responsibilities - Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design specifications are met. - Develop IP verification plans, test benches, and verification environments to ensure comprehensive coverage of mixed signal microarchitecture specifications. - Execute detailed verification plans, define and run system simulation models, analyze power and timing, and uncover bugs to optimize design functionality

- Debug issues in the presilicon environment through replication, root cause analysis, and implementation of corrective measures to resolve failing tests. - Collaborate with digital and analog architects, RTL developers, and physical design teams to enhance the verification of complex architectural and microarchitectural features. - Drive technical reviews of test plans and proofs with design and architecture teams, documenting all processes and findings

- Maintain and continually improve functional verification infrastructure, methodologies, and tools to align with evolving industry standards. Qualifications: Minimum Qualifications Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field. - 4-12 years of relevant experience -Proficiency in System Verilog,

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