Lead Senior Design Engineer – AI SoC Development
Intel · USA - CA - Folsom, United States
About this role
Job Details: Job Description: About the Role Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware
Position Overview You will develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence. You will apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation
Working closely with verification teams, you'll review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests. Additionally, you'll follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff. Key Responsibilities • Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations • Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs • Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design asp
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