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IP Design Verification Engineer

Samsung · SSIR, Goldstone, India

About this role

Position Summary About Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies

Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Design & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust)

Develop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios. Create reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects. Implement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness

Integrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow. Run and maintain regression suites on industry‑standard simul

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