IC Package Design / Development

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: IC Package Design / Development Role Overview We are seeking an experienced IC Packaging Engineer to drive next-generation package architecture, design, and productization using advanced node silicon (7nm, 5nm, 3nm and beyond). This role partners closely with chip design, system design, SI/PI, thermal, and manufacturing teams to define and deliver industry-leading package solutions

The ideal candidate has deep technical expertise in substrate design, floor-planning, bump architecture, advanced materials, and HVM execution. Key Responsibilities Package Architecture, Co-Design & Optimization Collaborate with chip design and analog/digital IP/PHY teams (224G/112G SerDes, PCIe Gen 6/7, ADC/DAC, etc.) to optimize chip floorplan, die bump patterns, and IO architecture for advanced node products. Co-optimize package stack-up, layer count, escape routing, BGA pattern, and power integrity architecture aligned to system and manufacturing requirements

Interpret SI/PI parameters (RL, IL, NEXT/FEXT, etc.) to drive signal integrity optimization. Package Design & Integration Work with IC design, system engineering, SI/PI, and thermal teams to perform BGA substrate design using Cadence APD or equivalent tools. Ensure package designs meet SI/PI, mechanical, high-power thermal and reliability targets

Define and refine assembly BOM, process flows, and design rules for advanced packaging technologies. Define POR for new silicon nodes including bump metallization, geometry, and process requirements. Drive implementation, optimization, and HVM qualification of new package / assembly technologies

Program Management & Cross-Functional Execution Own packaging deliverables from concept through substrate design, development, qualification, and high-

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