DFT Engineer

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom’s CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup

. You will also drive/push state of the art in the areas of testability, debug and quality, in order to aggressively deliver low DPPM's, while optimizing the cost for test. Responsibilities Drive the test quality of the products from Design to Production Participate/contribute in silicon bring-up, characterization, and silicon test Define and implement various DFx features Requirements Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, Loop-Backs etc.) covering digital logic domain, embedded memories and PHY/IO’s Scan flow development, ATPG pattern generation, verification and coverage analysis Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification Experience working with Cadence DFT tools (Modus and Genus) Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge Strong knowledge of logic & circuit design fundamentals is needed Working knowledge of TCL, perl Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a must Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc

is a plus Experience or familiari

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