DFT Engineer

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be working on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production

The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug, and yield improvement to meet the product test metrics. It involves working with the Physical Design and STA team for DFT mode timing closure. The role could also involve direct interaction with external customers

Responsibilities: Understanding Broadcom and customer DFT feature requirements, and DPPM goals and defining appropriate DFT specifications for the ASIC Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Pattern generation and verification at chip level, rapid bring-up at ATE and RMA support Working closely with STA and DI Engineers design closure for test Generating, verifying, and debugging test vectors before tape release Validating and debugging test vectors on ATE during the silicon bring up phase Assisting with silicon failure analysis, diagnostics, and yield improvement efforts Interfacing with the customer, physical design and test engineering/manufacturing teams located globally Working closely with I/P DFT engineers and other stakeholders Debugging customer returned parts on the ATE Innovating newer DFT solutions to solve testability problems in 3nm and beyond Automating DFT and test vector generation flows Skills/Ex

Apply for this role on Broadcom’s official careers site.