Design Engineer - Chip Floorplanner

About this role

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If you already have a Candidate Account, please Sign-In before you apply. Job Description: Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products

This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production. Role Overview This Floorplanning Engineer role focuses on chip-level physical architecture and integration for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs

Key Responsibilities Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning. Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization. Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets

Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness. Coordinate with block owners and integration teams for smooth block-level to top-level convergence. Support cross-functional design integration, providing guidance and technical support to internal and external partners

Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results. Contribute to design flow automation and methodology developmen

Apply for this role on Broadcom’s official careers site.