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Design Engineer – AI SoC Development

Intel · USA - CA - Folsom, United States

Engineering Engineering: General & Specialist Full-time Posted 5 days ago

About this role

Job Details: Job Description: Join Intel's AI Revolution Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware

What You'll Do As an RTL Design Engineer, you'll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features while performing quality checks across various logic design aspects from RTL to timing/power convergence. You'll apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation

Working closely with verification teams, you'll review verification plans and resolve failing RTL tests to ensure feature correctness. You'll follow secure development practices and collaborate with IP providers for SoC-level integration and validation. Key Responsibilities Architecture & Design • Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints • Implement RTL in Verilog/System Verilog based on defined micro-architecture • Integrate IP blocks at top level and ensure synthesis- and timing-clean design Verification & Validation • Work closely with verification teams to achieve full coverage and robust validation • Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks • Support silicon bring-up and post-silicon validation activities, including debug and performance analysis Collaboration & Quality • Collaborat

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